The present invention relates generally to semiconductor devices which handle relatively high-power and/or high current.
The most important phenomena which occurs at high-current levels is current crowding, that is, the crowding of the injected current toward the rim or the periphery of the emitter. The crowding of the injected current toward the rim of the emitter occurs primarily because a lateral potential gradient within the base layer is produced by the base current.
Consider the operation of a convention planar transistor such as illustrated in FIG. 1. FIG. 1 shows a cross-sectional view of a typical transistor structure such as produced by conventional methods. Regions of different conductivity type are labelled. The transistor comprises an N-type emitter region 11, a P-type base region 12, an N-type collector region 13, emitter ohmic contact 14 and base ohmic contact 15. It is to be understood that NPN and PNP structures are substantially equivalent in operation, and either may be employed. Since the base region 12 has a non-zero resistance and the base current 16 flows laterally within base region 12, a potential gradient is produced by the base current 16. Considering the polarity of the potential drop within base region 12, it becomes apparent that the rim 17 of the emitter region 11 is more forward-biased than the center 18 of the emitter region 11. This potential drop is not very large, but, since the injection increases exponentially with the voltage, its effect is magnified at high voltages. Hence, the emitter current is concentrated in a smaller area, i.e., the current density is larger at the rim 17. As a result, the rim 17 becomes hotter than center 18 due to the concentration of current carriers, reducing the power handling capacity of the transistor.
High power output transistors are therefore constructed in such a way to maximize the emitter periphery. Conventional power transistor design which aims to increase the emitter periphery is accompanied by an increase in the emitter area, the final chip size and, as a result, the chip cost.